1. Field of the Invention
The invention relates to the field of computer systems. More specifically, the invention relates to software debugging.
2. Background Information
Software debugging is the detecting, locating, and correcting of logical and/or syntactical errors in a computer program. Debug hardware is often included in a processor for use by a software debug program. Typically, the debug program uses the debug hardware to allow the programmer to examine data and check conditions during the execution of another computer program. Thus, the debugging features of a processor provide programmers with valuable tools for looking at the dynamic state of the processor.
A typical debug feature, when enabled, reports a debug event in response to a certain condition(s) being met. The term "event" is used herein to refer to any action or occurrence to which a computer system might respond (e.g., hardware interrupts, software interrupts, exceptions, faults, traps, aborts, machine checks, debug events). Upon recognizing an event, a processor's event handling mechanism causes the processor to interrupt execution of the current process, store the interrupted process'execution environment (i.e., the information necessary to resume execution of the interrupted process), and invokes the appropriate operating system handler. Upon completing the servicing of the event, the invoked handler instructs the processor to resume execution of the interrupted process using the previously stored execution environment. The appropriate handler for debug events is the debug handler. Thus, in response to each debug event, the debug handler is executed. The debug handler is a portion of the debug program and it allows the programmer to perform a variety of debugging techniques. When the programmer is finished, the programmer can cause the debug handler to instruct the processor to resume the interrupted process using the process' previously stored execution environment. Several different debug events may be serviced by a single handler.
One processor which includes debugging hardware is the Intel.RTM. 80960KB manufactured by Intel Corporation of Santa Clara, Calif. The 80960KB provides several debugging modes, including a "branch-trace mode" and an "instruction-trace mode." When the instruction-trace mode is enabled, the processor generates an instruction-trace event each time an instruction is executed. Debug software can use the instruction-trace mode to "single-step" the processor--i.e., interrupt execution after each instruction to allow the debug software to perform various debug techniques. When the branch-trace mode is enabled, the processor generates a branch-trace event each time an instruction that causes a branch (also termed as a "jump") to be taken is executed. An instruction that causes a branch to be taken is one that causes the processor to transfer flow of execution to another instruction (e.g., a jump instruction, a branch instruction, etc.). A taken branch typically transfers the flow of execution in a non-sequential manner--i.e., to an instruction which does not sequentially follow the instruction causing the branch to be taken. A branch-trace event is not generated for conditional-branch instructions that do not result in a branch being taken.
A register on the 80960 processor is used to store "trace controls" (flags for selecting between the different trace modes). This register also stores a trace-enable flag for enabling the trace modes selected by the trace controls. Typically, software selects the traces modes to be used through the trace controls and then sets the trace-enable flag when tracing is to be used. Upon recognizing an event, the processor interrupts execution of the current process, stores the interrupted process' execution environment (including the state of the trace-enable flag), disables the trace modes by clearing the trace-enable flag, and invokes the appropriate operating system handler. Upon completing the servicing of the event, the invoked handler instructs the processor to resume execution of the interrupted process using the previously stored execution environment (including the previous state of the trace-enable flag). Thus, the processor disables tracing during the execution of operating system routines which are called by the processor's event handling mechanism. As a result, the debug modes cannot be used to debug operating system routines as they are invoked by the event handling mechanism of the processor. Another limitation of the 80960KB processor is that is does not support address breakpoints.
Another processor which includes debugging hardware is the Intel Pentium.RTM. processor manufactured by Intel Corporation. The Pentium processor includes several debugging features, including a "single-step trap" and "address breakpoints." When enabled, a single-step trap occurs after the execution of the current instruction. Debug software can use the single-step trap to single step the processor. One limitation of this processor is that the INT instructions clear the TF flag. Therefore, software debuggers which single-step code must include complex algorithms to recognize and emulate INT n or INTO instructions rather than executing them directly. Due to this required emulation, the inclusion of new instructions may require the software debuggers to be rewritten. Another limitation of this processor is that additional circuitry had to be included to reconcile the single-step trap with the other events. This circuitry terminates single stepping if an external interrupt occurs. In addition, when both an external interrupt and a single-step interrupt occur together, this circuitry clears the TF flag, saves the return address or switches tasks, and examines the external interrupt input before the first instruction of the single-step handler executes. If the external interrupt is still pending, then it is serviced--i.e., that external interrupt's handler is executed. During the execution of the external interrupt's handler, the single-step trap is disabled. Upon completion of the external interrupt's handler, the processor returns to executing the single-step handler. Thus, operating system routines (such as the external interrupt handlers) are not normally run in single step mode. To run operating system routines in the single step mode, a INTn instruction which calls an interrupt handler must be single stepped. As a result, this processor does not allow single stepping to be enabled on operating system routines as they interact with other programs.
As previously stated, the Pentium processor also supports address breakpoints. The Pentium microprocessor includes 4 address breakpoint registers, each capable of storing the linear address of a breakpoint (i.e., the address of a memory or I/O location). Each of these breakpoint registers has two corresponding enable bits--a local enable bit and a global enable bit. These enable bits are used to enable and disable recognition of address breakpoints in relation to task switches. Task switching, also commonly referred to as multitasking, is the allocation of processing time between different programs executing on the processor. A task switch is like a procedure call, but it saves more processor state information. The Pentium processor supports both hardware task switching (also termed as protected-mode multitasking) and software task switching. Hardware task switches are performed by special hardware on the Pentium processor which stores nearly all of the processor's registers (e.g., the instruction pointer, status registers, general purpose registers, etc.) in memory. The local enable bits are automatically cleared by the processor with every hardware task switch to avoid unwanted breakpoint conditions in other tasks. In contrast, the global enable bits are not cleared by a hardware task switch. One limitation of hardware task switching is that it requires microcode.
Future processors may not include microcode. Another limitation of hardware task switching is that it saves nearly all the processor's registers, whether or not they need to be saved. This unnecessary saving of information degrades the processor's performance.
In contrast, a software task switch is one in which the hardware on the processor stores the minimum information necessary (e.g., the instruction pointer and some status registers) to resume the previous task and the software determines whether it is necessary to store the rest. Software task switches can be used to optimize performance by allowing smaller processor states to be saved. For a further description of the Pentium processor see: Pentium Processor's Users Manual Users Manual-Volume 3: Architecture and Programming Manual, 1994, available from Intel Corporation of Santa Clara, Calif. A limitation of the Pentium microprocessor is that neither the local enable bits nor the global enable bits are cleared by software task switches. As a result, recognition of an address breakpoint is either enabled or disabled during execution of both applications and invoked operating system routines when software tasks switches are used. For example, a programmer could not enable recognition of an address breakpoint only during the execution of operating system handlers. To recognize an address breakpoint, comparing circuitry (typically a comparator) is used. Since the Pentium processor is superscalar (i.e., it allows for the execution of multiple instructions per clock cycle, each instruction being executed by a separate pipeline), an address breakpoint could be generated by the execution of any one of the instructions. To avoid the inclusion of comparing circuitry in every pipeline, the Pentium processor operates in a scalar mode (i.e., using only one pipeline--executing only one instruction per clock cycle) while address breakpoints are enabled. Thus, the Pentium processor trades cost and complexity for a degradation in performance when using address breakpoints.
Typically, programmers are debugging either an application or an operating system. However, when address breakpoints are enabled and software task switches are used, recognition of address breakpoint events is enabled and the processor operates in the scalar mode during the execution of both applications and the operating system. As a result, the Pentium is unnecessarily degraded when using address breakpoints. This is especially problematic when debugging software on a multi-user system. Another limitation of the Pentium processor is that it does not support branch breakpoints.